In a technique of a layout design of an LSI circuit, the need of a method of supporting a layout design increases in which the timing convergence can be attained without increasing TAT (Turn Around Time) with increase of a circuit scale and operation speed in the LSI circuit.
Patent Literature 1 (especially, reference to FIG. 3 and page 2) describes a technique for sufficiently shortening TAT by a hierarchy layout design method in case of development of an LSI circuit. In this technique, preprocessing is carried out to extract a timing error path from the result of flat arrangement and wiring in the whole LSI circuit through STA (Static Timing Analysis) in case of dividing a net list of the LSI circuit into layers. After that, a region which contains a timing error path is divided into hierarchy layout blocks (HLBs) and a layer layout is attained every HLB.
FIG. 1A and FIG. 1B are a flow chart showing a procedure of Patent Literature 1. Arrangement and wiring processing and timing analysis processing are carried out based on a flat physical design data of the whole LSI circuit (Step S1). A path where a timing error has occurred is extracted (Step S2). A region which contains the extracted path is divided into hierarchy layout blocks (HLBs) (Steps S3 to S7). A timing constraint is divided every HLB (Step S8). A layout is carried out every HLB based on the timing constraint (Steps S9 to S11). A flat physical design data is generated by combining laid HLB data (Step S12).